The present invention relates to a dual port random access memory (RAM) and, more particularly, to a dual port RAM having shadowing capabilities to facilitate communication between two devices.
Heretofore, system designers have allowed two intelligent devices, such as controllers or processors, to communicate with one another. The use of random access memory has facilitated such communication or data transfer between devices. In other words, one device can generate data that the second device uses. Bidirectional communication is, of course, also necessary with a RAM, so that the second device can generate data when the first device is the recipient thereof.
The use of random access memory also allows data to be updated, either by the originating device or by the receiving device at a later time.
To solve the problem of data access by two devices concurrently or approximately concurrently, dual port RAM have been developed. The dual port RAM of the prior art, however, has certain drawbacks, including potential for significant access time penalties due to the fact that one device must finish writing data into a location before the second device attempts to do so or before the second device attempts to read the data.
Contention problems occur when both devices write, or when one device reads while the other device attempts to write, to the same location in memory. Generally, and fortunately, contention does not exist when two devices attempt to read the same data. Moreover, determining which device should get access to the memory (i.e., arbitration) and determining the length of delay required before a given device is allowed access to memory may also be significant, time consuming factors.
The amount of data access required of a RAM device during any period of time is uncertain. Record keeping, testing and the like can occur before a device is allowed to access memory previously updated by the other device. The prior art teaches the use of certain control signals, such as READY and ACKNOWLEDGE, to keep track of access interleaving 1rom the devices.
Another problem occurs when two disparate devices are used with one dual port RAM. The dual port RAM generates certain control signals that may not be suitable for all devices that access data stored in RAM. Accordingly, so called "glue logic" is required to smooth the transition between data generated by one controller and accessed by another or for data that is to be accessed by two or more controllers.
It would be advantageous to interface two or more devices such as processors to one another in a simple system design.
It would also be advantageous to facilitate communications between two devices by use of a dual port RAM.
It would also be advantageous to provide a dual port RAM that would allow two devices to access data therein approximately simultaneously.
It would also be advantageous to eliminate control signals when accessing data in predetermined memory locations of RAM.
It would also be advantageous to eliminate glue logic and other measures conventionally required to allow two disparate devices to communicate with one another.
It would also be advantageous to provide a mechanism for updating data stored in a dual port RAM so as to facilitate access to the updated data by disparate devices connected thereto.
It would also be advantageous to provide a dual port RAM with relatively high operating speeds and low costs.
It would also be advantageous to provide a system that includes a fixed access time for devices with synchronized bus cycles to interface to RAM.
It would also be advantageous to provide a dual port RAM, one device and the interface means therefor on a single IC chip.